Scatter And Gather

Master memory fragmentation: Build a smart FIFO for many queues, one memory!

PROBLEM STATEMENT:
Often in blocks of logic that handle network interfaces, it is common to store packets in a temporary buffer before the CPU can process them. However, long chunks of free contiguous memory is a luxury that isn’t available in most settings. To deal with fragmented memory layouts like this, a scatter-gather approach is commonly used by DMAs and FIFOs handling network interfaces.

In this problem we once again build a FIFO but with some very interesting requirements. The FIFO memory shall be shared by 64 independent queues of 32-bit data width each. The system ensures that the combined data of all the 64 queues does not exceed 4K words of data. (To further clarify, this DOES NOT mean the size of a single queue can be 64 words at max. It means that you could have any combination between 1 queue occupying the entire memory or 64 queues of 64 words each occupying the memory).

Apart from the usual FIFO related interface signals, we get a queue ID as the input, which allows us to push to and pop from the right queue.

The testbench also lets you perform any memory initialization in case you need it. For this, the interface gives you a “fifo_init_done_o” signal that needs to be driven HIGH and stay there for the testbench to start testing. If your design has no need to perform initialization, feel free to tie this output to HIGH. Note that once HIGH, this signal should never go low unless it is reset by the testbench. Doing so will cause the test case to fail.

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Interface Definition

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