Atomic Counters

Divide by 3

3-bit Palindrome

Sequence Generator

Single Cycle Arbiters

Events to APB

Low Power Channel

Two Pulses

Clock Generator

Skid Buffer

Least Recently Used

Edge Capture

One Shot

Parallel to Serial

Running Average

Big Endian Converter

Credits & Deadlock

Ordering

Performance Counter

Asynchronous Resets

Fifo Flush

Buffering

Compression Engine

Perfect Squares

Cross correlation

System Verilog for Design

Data Muxing

Fast Fifo

Find First Set

Packet Decoder

Complex Packet Decoder

You are working on implementing a data muxing logic for a NoC router. The logic takes in data
from N multiple sources and forwards it to a single destination based on the select signal.

Given this scenario, you decided to pass this information to your in-house AI agent to generate
the RTL code for the data muxing logic. The agent generated the logically correct code but the
Physical Design team is complaining of timing pressure on the muxed data output.

Fix the data muxing module to ease the timing pressure on the muxed data output. All the flops
should be positive edge triggered with asynchronous resets (if any).

## Interface Definition
```
data_i : Input DATA_WIDTH wide data from the N sources
one_hot_sel_i : One-hot select signal to select the source for muxing

mux_data_o : Muxed DATA_WIDTH wide data output
```

## Interface Requirements
- Muxing output needs to be given in the same cycle as when the data and select signals are provided
- The select signal will be one-hot or zero, meaning at most only one source will be selected at a time
