Introduction

Running Simulations

Combinatorial Logic

Sequential Logic

D Flip-Flop

D Flip-Flop with Enable

Counter

Up-down Counter

Self Reloading Counter

Shift Register

A simple 2:1 mux is the hardware equivalent for the Hello World program. This example
shows how to implement a 2:1 mux from scratch using System Verilog.

## Interface Definition
`a`   : First input to the mux
`b`   : Second input to the mux
`sel` : Mux select line
`y`   : Mux output

## Note
Please use System Verilog as the selected language. The support for other languages might be broken.


## System Verilog

```verilog
// --------------------------------------------------------
// Copyright (C) quicksilicon.io - All Rights Reserved
//
// Unauthorized copying of this file, via any medium is
// strictly prohibited
// Proprietary and confidential
// --------------------------------------------------------

// --------------------------------------------------------
// Mux - RTL
// --------------------------------------------------------

module mux2to1 (
  input   logic a,
  input   logic b,
  input   logic sel,
  output  logic y
);

  // sel == 0 -> y = a
  // sel == 1 -> y = b
  assign y = sel ? b : a;

endmodule

```

-----------
## Verilog

```verilog
// --------------------------------------------------------
// Copyright (C) quicksilicon.io - All Rights Reserved
//
// Unauthorized copying of this file, via any medium is
// strictly prohibited
// Proprietary and confidential
// --------------------------------------------------------

// --------------------------------------------------------
// Mux - RTL
// --------------------------------------------------------

module mux2to1 (
  input   wire a,
  input   wire b,
  input   wire sel,
  output  wire y
);

  // sel == 0 -> y = a
  // sel == 1 -> y = b
  assign y = sel ? b : a;

endmodule

```

-----------
## VHDL

```vhdl
-- --------------------------------------------------------
-- Copyright (C) quicksilicon.io - All Rights Reserved
--
-- Unauthorized copying of this file, via any medium is
-- strictly prohibited
-- Proprietary and confidential
-- --------------------------------------------------------
--
-- --------------------------------------------------------
-- Mux - RTL
-- --------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity mux2to1 is
  port (
    a   : in  std_logic;
    b   : in  std_logic;
    sel : in  std_logic;

    y   : out std_logic
  );
end mux2to1;

  -- --------------------------------------------------------
  -- Internal wire and regs
  -- --------------------------------------------------------
  architecture logic of mux2to1 is

    begin
      y <= a when sel = '0' else b;

  end architecture;
```
