Verification
Simulation
The process of executing a hardware model to verify behavior before physical implementation.
Detailed Explanation
Simulators execute HDL code, computing signal values over time. Event-driven simulation updates signals only when inputs change. Cycle-accurate simulation evaluates at clock edges. Waveform viewers display signal transitions.
Testbenches drive inputs and check outputs. Simulation catches functional bugs but cannot guarantee correctness—it only checks tested scenarios. Simulation speed limits the number of test cases feasible.