Digital Logic
Multiplexer (MUX)
A combinational circuit that selects one of multiple inputs and routes it to a single output based on select signals.
Detailed Explanation
A 2-to-1 mux has two data inputs, one select, and one output. The select signal chooses which input appears at output. Larger muxes (4:1, 8:1, etc.) use additional select bits. Muxes are fundamental for data routing and conditional operations.
Muxes implement conditional expressions (sel ? a : b). Chains of muxes implement priority logic or case statements. Wide muxes in timing-critical paths may use tree structures for better delay.
Code Example
systemverilog
// 2-to-1 multiplexer
module mux2to1 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] a, b,
input logic sel,
output logic [WIDTH-1:0] y
);
assign y = sel ? b : a;
endmodule
// 4-to-1 multiplexer
always_comb begin
case (sel)
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
2'b11: y = d;
endcase
end