APB Transaction

In the last module we discussed the APB System RTL which is our design under test. We also implemented the SystemVerilog based interface to communicate between the RTL and the Testbench. In this module we would look into the first class based component - the Transaction Class.

Transaction Class

As we make progress towards the testbench architecture, the first component is the transaction class. The transaction class will be used to create random stimulus for our testbench. Since the testbench would be responsible for driving all the inputs to the design, the transaction class should be able to randomize all of the input signals while up-holding all the constraints which may apply to any of the signals.

Testbench_Architecture

This would imply that the following input signals should be randomized along with any constraints:

• prdata : The read data from the slave
• pready : Indicates the slave has accepted the request

Given there were no constraints on the read data from the slave and the pready indication, the transaction class should be able to randomize both the signals without adding any constraints.