Verification

Transaction

A high-level object representing one protocol operation, such as a read, write, packet, or command, used by verification components instead of raw signal toggles.

Detailed Explanation

A transaction abstracts away pin-level activity into a meaningful protocol event. Instead of thinking in terms of `psel`, `penable`, `paddr`, and `pwdata` every cycle, the testbench represents an APB write as one transaction object containing address, data, and direction. Drivers convert transactions into waveform-level stimulus, and monitors reconstruct transactions back from observed signals.

This abstraction is what makes verification environments scalable. Once a protocol operation becomes a reusable object, it can be randomized, queued, cloned, logged, and checked much more easily than raw signals. Transaction-level thinking is also the bridge between lightweight Verilog testbenches and more structured methodologies like UVM.

Code Example

systemverilog
class apb_txn;
  logic [31:0] addr;
  logic [31:0] data;
  logic        write;
endclass