Constraint Randomization
A SystemVerilog verification technique where random stimulus is generated subject to user-defined constraints.
Detailed Explanation
Constraint randomization gives a testbench a way to explore many legal input combinations without hand-writing every case. Instead of enumerating transactions one by one, the verification engineer defines rules such as address ranges, legal burst lengths, alignment requirements, or protocol relationships between fields. The simulator then solves those constraints to produce randomized but valid stimulus.
This approach is powerful because it combines breadth with control. Purely directed tests are easy to reason about but narrow; unconstrained random tests are broad but often useless. Constrained-random testing sits in the middle, allowing the environment to stress a DUT across a large space while still honoring protocol rules and focusing on interesting corner cases.
Code Example
class apb_txn;
rand logic [31:0] addr;
rand logic [31:0] data;
rand logic write;
constraint word_aligned_c { addr[1:0] == 2'b00; }
constraint cfg_space_c { addr inside {[32'h0000_0000:32'h0000_00FF]}; }
endclass