SystemVerilog Testbench Introduction

SystemVerilog Testbench Architecture

APB Interface

APB Transaction

APB Generator

APB Driver

APB Driver Phase 2

APB Monitor

APB Scoreboard

APB Environment

APB Testbench Top

RISC-V Processor (YARP) Interface

YARP Transaction

YARP Generator

YARP Driver

YARP Data Memory Model

YARP Monitor

YARP Scoreboard

YARP Testbench Top

DVCon 26 Hackathon Problem

Array Sum Limit

Array Index Sum Limit

Ball Draw No Repeat

Conditional Even Probability

Even Odd Index Value

Five Consecutive Ones

Frequency Constraint

Grouped Ones

Index Value Range

Leap Year

Matrix Rotation

Non Adjacent Ones

Power of 4

Dynamic Ranges

Recent Four Unique

Row Max Unique

Subarray Max Sum

Three Duplicates Only

Tic Tac Toe

Unique 3D Array

Weighted Popcount

Unique Sum

Split Array into Queues

Welcome to the course on Testbench Design using SystemVerilog. In this practical hands-on course we
would explore SystemVerilog to design dynamic class based testbenches from the grounds-up. The course
would explore the design of the testbenches for verifying the following:

- APB Master System
- Single-cycle RISC-V CPU

### This is a hands-on course which means you would be spending more of your time coding various testbench components.

This module would give you an introduction to the common testbench architecture. It would include the description of
how modern testbenches are built using various components and how ultimately they all tie together to validate the
design under test (DUT). The video explains the overall testbench architecture and then explains the role for each
of the following components:

- Transaction
- Generator
- Driver
- Monitor
- Scoreboard
- Agent
- Environment
- Testbech top module

As you can see from the image below, each of these components together build a testbench which validates the RTL.
![Testbench_Architecture](/Testbench_Arch.webp)

## Coding Exercise
In the previous module, there was no waveform generated since there was no RTL and the testbench also finished at time 0 itself.
In this module we would improve the testbench to generate the clock and drive a signal to the instantiated RTL. The RTL implements
a simple D flip-flop and the testbench would toggle the D-pin randomly. Make sure to view the waveforms to see the bits toggling.

The video for this module also includes a detailed explaination of the testbench covering each line. Do watch the video to
get a better understanding of the testbench code. As always, you could reach out to me via [email](mailto:info@quicksilicon.in) or [discord](https://discord.gg/f3TpbQdtH8Text)
if you have any further doubts and I'd be happy to help!


Welcome to the course on Testbench Design using SystemVerilog. In this practical hands-on course we
would explore SystemVerilog to design dynamic class based testbenches from the grounds-up. The course
would explore the design of the testbenches for verifying the following:

- APB Master System
- Single-cycle RISC-V CPU

### This is a hands-on course which means you would be spending more of your time coding various testbench components.

This module would give you an introduction to the common testbench architecture. It would include the description of
how modern testbenches are built using various components and how ultimately they all tie together to validate the
design under test (DUT). The video explains the overall testbench architecture and then explains the role for each
of the following components:

- Transaction
- Generator
- Driver
- Monitor
- Scoreboard
- Agent
- Environment
- Testbech top module

As you can see from the image below, each of these components together build a testbench which validates the RTL.
[Testbench_Architecture](/public/testbench_arch.webp)

## Coding Exercise
In the previous module, there was no waveform generated since there was no RTL and the testbench also finished at time 0 itself.
In this module we would improve the testbench to generate the clock and drive a signal to the instantiated RTL. The RTL implements
a simple D flip-flop and the testbench would toggle the D-pin randomly. Make sure to view the waveforms to see the bits toggling.

The video for this module also includes a detailed explaination of the testbench covering each line. Do watch it if the code doesn't
make sense. As always, you could reach out to me via [email](mailto:info@quicksilicon.in) or [discord](https://discord.gg/f3TpbQdtH8Text) if you have any further doubts and I'd be happy to help!


# Class
```verilog
class sv_testbench_arch;

  // Declare a random variable of type bit as the d-pin to DFF
  rand bit d;

  function new ();
    $display("%t\tHello from sv_testbench_arch", $time);
  endfunction

  // Function to get the random value of d
  // NOTE: The bit d gets a random value each time this function is called
  function bit get ();
    void'(this.randomize());
    return d;
  endfunction

endclass

```

# Top Module
```verilog
`timescale 1ns/1ps
// --------------------------------------------------------
// SV Testbench - Top Module
// --------------------------------------------------------

module sv_testbench_arch_top ();

  // --------------------------------------------------------
  // Testbench signals
  // --------------------------------------------------------
  logic clk;
  logic reset;

  logic d;
  logic q;

  // --------------------------------------------------------
  // Instantiate the RTL
  // --------------------------------------------------------
  dff  DFF (
    .clk          (clk),
    .reset        (reset),
    .d_i          (d),
    .q_o          (q)
  );

  // --------------------------------------------------------
  // Create the object
  // --------------------------------------------------------
  sv_testbench_arch sv_testbench_arch_obj;

  // Instantiate the object once in the initial block
  initial begin
    sv_testbench_arch_obj = new();
  end

  // --------------------------------------------------------
  // Generate the stimulus
  // --------------------------------------------------------
  // Generate stimulus for the DUT using the always block
  always begin
    d <= 1'b0;

    // Reset Sequence
    reset <= 1'b1;
    // Wait for 2 cycles
    @(posedge clk);
    @(posedge clk);
    // Release the Reset
    reset <= 1'b0;

    // Generate stimulus for 32 cycles
    repeat (32) begin
      @(posedge clk);
      d <= sv_testbench_arch_obj.get();
    end

    // End the simulation
    $finish;
  end

  // --------------------------------------------------------
  // Generate the clock
  // --------------------------------------------------------
  always begin
    clk <= 1'b1;
    #5;
    clk <= 1'b0;
    #5;
  end

  // --------------------------------------------------------
  // Dump the waveform
  // --------------------------------------------------------
  initial begin
    $dumpfile(`QS_VCD_DUMP_NAME);
    $dumpvars(0, sv_testbench_arch_top);
  end

endmodule
```
