SystemVerilog Testbench Introduction

Welcome to the course on Testbench Design using SystemVerilog. In this practical hands-on course we would explore SystemVerilog to design dynamic class based testbenches from the grounds-up. The course would explore the design of the testbenches for verifying the following:

• APB Master System
• Single-cycle RISC-V CPU

This course would cover all the aspects of testbench design from discussing the RTL functionality and the interface requirements all the way to implementing each of the different testbench components. The testbench would be designed using vanilla SystemVerilog without using any libraries. At the end of the course you would have built the testbench from scratch to verify the APB Master System and the Single-cycle RISC-V CPU.

This is a hands-on course which means you would be spending more of your time coding various testbench components.

The pane on the right contains two files to run a simple welcome messasge. The top module in the program instantiates and creates the class object which has the display message as part of its new() method. Try running the program by clicking on the Run Testcases button to see the message displayed.

FAQs:

What this course will teach?

• This course will teach you the fundamentals behind the testbench design and how modern day testbenches built from the grounds up
• The course would cover step-by-step hands-on guide to build testbenches for different designs. This would include the following modules:
  • RTL Design overview and interface requirements
  • Implementing the transaction object for the given interface
  • Implementing testbench components like driver, monitor, scoreboard, agents, etc from scratch
  • Implementing the random stimulus by using SystemVerilog constraints
  • Adding C-based checkers using DPI for the RISC-V CPU model and integrating it with the testbench
• The course is broken into several modules covering the finer details for every step of the testbench design

What projects would you be able to cover through this course?

• Through this course you would able to implement testbenches for two fairly complex designs:
  • APB Master System: This involves designing a TB to verify an APB master system with certain interface requirements
  • RISC-V CPU: In this module you would implement the entire testbench to verify a single cycle RV32I compliant CPU

What isn't covered in this course?

• This course doesn't necessarily teach the basics of object oriented programming or various SystemVerilog features for Verification
• The course does provide some introduction to cover crucial concepts when they are used while designing the testbench component
• This course does not cover the Universal Verification Methodology (UVM) - All the class based components use pure SystemVerilog

What can be the next steps for someone who has successfully completed this course?

• This course would teach you the fundamentals of building testbenches from scratch with two fairly complex projects
• As a next step, this course could be your way to learning UVM and could use the projects from this course and convert them into UVM
• You could implement more testbenches (trust me, the more you practice the better you get)
  • Pick a hard problem from the Hands-on RTL Design course and challenge yourself to implement the testbench for it
  • I would be more than happy to review your implementation and provide feedback!

What are the pre-requisites for this course?

• Some basic understanding of SystemVerilog and the various verification features is required
  • If you understand what is meant by classes, what is a constraint, etc - then you should be good to go!
• Some exposure to understanding RTL (written in SystemVerilog) would be desired but is not absolutely required for this course