Verification
Testbench
A simulation environment that drives inputs to a design under test (DUT) and checks its outputs for correctness.
Detailed Explanation
Testbenches instantiate the DUT, generate stimulus (input patterns), and verify outputs match expected behavior. Simple testbenches apply directed tests; advanced testbenches use constrained random generation, scoreboards, and coverage collection.
Testbenches are not synthesized—they use behavioral constructs freely. SystemVerilog UVM provides a standardized methodology for complex testbenches with reusable components.
Code Example
systemverilog
// Simple testbench structure
module tb_counter;
logic clk, reset;
logic [3:0] count;
// Instantiate DUT
counter dut (.clk(clk), .reset(reset), .count(count));
// Clock generation
initial clk = 0;
always #5 clk = ~clk;
// Test stimulus
initial begin
reset = 1;
#20 reset = 0;
#100;
// Check count value
if (count != 4'd10)
$error("Count mismatch: expected 10, got %d", count);
$finish;
end
endmodule