YARP Driver

In this module, we would implement the driver class to get the transaction from the generator mailbox and use it to toggle the input pins of our RISC-V CPU. The driver class allows the testbench to drive the randomized stimulus to the DUT while ensuring that all the input constraints specified by the DUT are indeed met.

The YARP DUT has two valid/ready based interfaces: the Instruction memory interface and the Data memory interface. Since this is a single cycle implementation of the RISC-V CPU, the instruction memory interface and the data memory interface are closely coupled. The data memory interface is only valid when the instruction is either a load or a store instruction which then asserts the request on the data memory interface. The instruction memory interface waits for the data memory interface to be ready before it can assert the request for the next instruction. Given the relationship between the two interfaces, we will build a single agent to handle the two interfaces. The driver class would be responsible for driving the ready signals of both of these interfaces and as well as the data signals. However, if we look into the transaction object, it gives us the following information:

• instr_mem_ready_delay: The delay in clock cycles before the instruction memory interface is ready
• data_mem_ready_delay: The delay in clock cycles before the data memory interface is ready

Given these are the delays before the interfaces are ready, the driver class would need to wait for a valid transfer on each of the interfaces, and then assert the ready on the respective interfaces after waiting for the respective delays. Let's try to implement the driver class to handle this.

Testbench_Architecture