Verification

Driver

A testbench component that consumes transaction objects and drives them onto the DUT's interface pins according to the protocol timing.

Detailed Explanation

The driver is the inverse of the monitor. It pulls transactions from a mailbox — typically produced by a generator or sequencer — and translates each into the exact signal activity the DUT expects: correct setup times, the right handshake sequence, legal address ranges. For APB, a write transaction becomes a `psel`→`penable` two-cycle exchange; for AXI, it may involve separate address, data, and response channels with independent ready/valid handshakes.

Protocol-correctness is what separates a robust driver from a source of false failures. Good drivers use clocking blocks to avoid race conditions on every sampled signal, time stimulus to the negedge or a well-defined skew, and never drive pins outside of the protocol's legal states — even in error-injection mode, the illegal behavior is the *stimulus*, not an accident of timing.

Code Example

systemverilog
class apb_driver;
  virtual apb_if vif;
  mailbox #(apb_txn) in_mbx = new();
  task run();
    apb_txn t;
    forever begin
      in_mbx.get(t);
      @(posedge vif.clk);
      vif.psel    <= 1;
      vif.paddr   <= t.addr;
      vif.pwrite  <= t.write;
      vif.pwdata  <= t.data;
      vif.penable <= 0;
      @(posedge vif.clk);
      vif.penable <= 1;
      wait (vif.pready);
      @(posedge vif.clk);
      vif.psel    <= 0;
      vif.penable <= 0;
    end
  endtask
endclass