SystemVerilog Testbench Introduction

SystemVerilog Testbench Architecture

APB Interface

APB Transaction

APB Generator

APB Driver

APB Driver Phase 2

APB Monitor

APB Scoreboard

APB Environment

APB Testbench Top

RISC-V Processor (YARP) Interface

YARP Transaction

YARP Generator

YARP Driver

YARP Data Memory Model

YARP Monitor

YARP Scoreboard

YARP Testbench Top

DVCon 26 Hackathon Problem

Array Sum Limit

Array Index Sum Limit

Ball Draw No Repeat

Conditional Even Probability

Even Odd Index Value

Five Consecutive Ones

Frequency Constraint

Grouped Ones

Index Value Range

Leap Year

Matrix Rotation

Non Adjacent Ones

Power of 4

Dynamic Ranges

Recent Four Unique

Row Max Unique

Subarray Max Sum

Three Duplicates Only

Tic Tac Toe

Unique 3D Array

Weighted Popcount

Unique Sum

Split Array into Queues

Congratulations on making it this far! This would be the final module for the YARP CPU testbench.
This module will include the environment class and as well as the testbench top module.
The environment class is responsible for building the agent and the scoreboard and then calling the respective `run()` tasks.
The testbench top level has the following responsibilities:

- Instantiate the design under test
- Create and instantiate the actual interface which would connect the DUT and TB
- Create the environment class and start it by calling the `run()` method
- Generate clocks which would be passed to both the testbench and the DUT
