Protocols
Burst Transfer
A bus transaction that transfers multiple data words using a single address phase, improving throughput efficiency.
Detailed Explanation
Instead of sending address-data pairs for each word, burst transfers send one address followed by multiple consecutive data beats. The address typically auto-increments. Burst types include incrementing (sequential addresses), wrapping (for cache lines), and fixed (same address repeated for FIFOs).
Bursts amortize address overhead and allow memory to exploit row locality. AXI supports burst lengths up to 256 beats. Burst transactions must be designed carefully—a long burst can block other traffic.