Semiconductor Glossary

A combinational circuit that performs arithmetic addition of binary numbers.

A set of parallel signal lines used to specify memory or I/O locations for read/write operations.

A combinational circuit that performs arithmetic and logical operations on binary data.

ARM's open standard for on-chip interconnect specification, including APB, AHB, and AXI protocols.

The SystemVerilog interface construct that bundles the APB signal set so masters, slaves, and testbench components can connect through a single handle.

The APB agent that initiates transactions — drives address, data, and control signals, and waits for the slave's ready.

A low-complexity AMBA protocol designed for low-bandwidth peripheral access with minimal power consumption.

The APB agent that responds to the master — decodes the address, returns read data, accepts writes, and drives the ready signal.

A circuit that manages access to a shared resource among multiple requestors, granting access based on a priority or fairness scheme.

A custom-designed integrated circuit optimized for a specific application rather than general-purpose use.

A statement in verification code that checks whether a design property holds true during simulation or formal analysis.

A digital circuit that operates without a global clock signal, using handshaking or other mechanisms for synchronization.

A reset signal that immediately forces registers to their initial state regardless of clock state.

An operation that completes entirely without interruption, appearing instantaneous to other observers in the system.

A high-performance AMBA protocol supporting multiple outstanding transactions, out-of-order completion, and separate read/write channels.

A flow control mechanism where a receiver signals that it cannot accept more data, causing the sender to pause transmission.

A combinational circuit that can shift or rotate data by any number of positions in a single cycle.

A circuit that swaps byte order to convert between big-endian and little-endian data formats.

A base-2 number system using only digits 0 and 1, fundamental to digital electronics.

The smallest unit of digital information, representing a single binary value of 0 or 1.

A SystemVerilog assignment (=) that executes sequentially, completing before the next statement begins.

Mathematical system for analyzing and simplifying logic expressions using AND, OR, NOT operations and their laws.

The logic that decides whether a branch instruction is taken and computes the resulting program counter.

A technique where processors guess the outcome of conditional branches before they're resolved to maintain pipeline flow.

A circuit that isolates input from output, provides drive strength, or stores data temporarily.

Techniques for storing data temporarily between pipeline stages or interfaces operating at different rates.

A bus transaction that transfers multiple data words using a single address phase, improving throughput efficiency.

A shared communication pathway connecting multiple components, allowing data transfer between them.

A unit of digital information consisting of 8 bits.

A small, fast memory that stores copies of frequently accessed data to reduce average access time.

Protocols ensuring all processors see a consistent view of shared memory despite having private caches.

The fixed-size block of memory data that a cache stores and transfers as a single unit.

The staged implementation of cache access logic so tag lookup, data read, and hit/miss handling can meet timing at higher clock frequencies.

The output generated when the sum of binary digits exceeds the column's capacity, propagating to the next column.

A small fixed-width value computed from a block of data and sent alongside it so the receiver can detect corruption.

A periodic signal that synchronizes operations in a digital circuit, triggering state changes on its edges.

The interface between two parts of a design operating on different clocks, requiring special synchronization.

A power-saving technique that disables the clock to idle circuit blocks, eliminating switching power.

A Python-based verification framework that enables writing testbenches in Python rather than HDL.

A circuit whose output depends only on current inputs, with no memory or feedback.

A circuit that compares two binary values and outputs their relationship (equal, greater than, less than).

A hardware block that reduces data size using algorithms like run-length encoding or dictionary-based compression.

A SystemVerilog verification technique where random stimulus is generated subject to user-defined constraints.

The combinational block that decodes an instruction's opcode into the control signals that drive the datapath.

A sequential circuit that cycles through a sequence of states, typically incrementing or decrementing a binary value.

Metrics measuring how thoroughly a testbench exercises the design, indicating verification completeness.

A flow control mechanism where the sender tracks available receiver buffer space using credits, sending data only when credits are available.

A measure of similarity between two signals as a function of displacement, used for pattern matching and synchronization.

An interconnect that allows any input to connect to any output simultaneously, enabling parallel transfers.

A fundamental memory element that captures its data input on a clock edge and holds the value until the next clock edge.

A set of parallel signal lines carrying data between components in a digital system.

The memory region that holds program data, accessed via load and store instructions in the memory stage.

The part of a cache pipeline that reads, aligns, and returns the actual data stored in cache lines.

A system state where circular dependencies prevent any progress, with each component waiting for resources held by others.

A combinational circuit that converts a binary input code into a one-hot output, activating exactly one output line.

A circuit that routes a single input to one of many outputs based on a select signal.

A mechanism allowing peripherals to transfer data directly to/from memory without processor intervention.

A condition where the output value doesn't matter, allowing synthesis tools freedom to optimize.

A testbench component that consumes transaction objects and drives them onto the DUT's interface pins according to the protocol timing.

Memory that supports simultaneous access from two independent ports, each with its own address and data interface.

A circuit that detects transitions (rising edge, falling edge, or both) on an input signal.

A combinational circuit that converts a one-hot or binary-active input to a compact binary code.

The convention determining byte ordering when storing multi-byte values in memory.

The top-level verification container that connects generators, drivers, monitors, scoreboards, and other testbench infrastructure around a DUT.

The number of inputs to a logic gate, affecting its propagation delay and drive capability.

The number of gate inputs driven by a single gate output, affecting signal integrity and timing.

A buffer that stores data elements and retrieves them in the order they were written.

A sequential circuit with a finite number of states, transitioning between states based on inputs and producing outputs.

A bistable circuit that stores one bit of data, changing state on clock edges.

Mechanisms that regulate data transmission to prevent overflow when receiver can't keep pace with sender.

An integrated circuit that can be programmed after manufacturing to implement digital logic.

The number of clock cycles per second, measured in Hertz (Hz), determining system speed.

A combinational circuit that adds three single bits (two operands plus carry-in) producing sum and carry-out.

A fundamental digital circuit element that performs a basic Boolean operation on one or more inputs.

A testbench component that creates transaction objects and feeds them to downstream components such as drivers or sequencers.

A brief, unwanted signal transition caused by unequal propagation delays through combinational logic paths.

A binary encoding where consecutive values differ by exactly one bit, minimizing transition errors.

A combinational circuit that adds two single bits, producing a sum and carry output but no carry input.

A synchronization protocol where communicating parties exchange signals to coordinate data transfer.

A specialized language for describing digital circuit structure and behavior, used for simulation and synthesis.

A condition where circuit behavior differs from expected due to timing or structural issues.

A base-16 number system using digits 0-9 and A-F, providing compact representation of binary values.

The minimum time a data signal must remain stable after the clock edge for reliable flip-flop capture.

A single operation command in a processor's ISA, specifying an operation and its operands.

The pipeline stage that interprets an instruction's bit fields to extract the opcode, register specifiers, and immediate values.

The first pipeline stage of a processor, where the next instruction is read from instruction memory using the program counter.

The memory region that stores a program's instructions, addressed by the program counter during fetch.

An asynchronous signal that diverts processor execution to handle an event requiring attention.

A logic gate that produces the complement (NOT) of its input—0 becomes 1, 1 becomes 0.

The abstract interface between hardware and software, defining instructions, registers, and programming model.

An industry standard for testing and debugging integrated circuits through a serial interface.

A graphical method for simplifying Boolean expressions by grouping adjacent terms in a grid.

A level-sensitive storage element that passes input to output when enabled and holds when disabled.

The time delay between initiating an operation and receiving the result.

The bit position with the smallest weight (2⁰) in a binary number, typically the rightmost bit.

A condition where processes continuously change state in response to each other but make no progress.

A physical device implementing a Boolean function with one or more inputs and one output.

Design techniques that minimize power consumption while meeting performance requirements.

A legacy bus protocol using few pins for low-speed peripheral communication, common in PC motherboards.

A cache replacement policy that evicts the cache line accessed longest ago.

An FPGA primitive that implements any Boolean function of its inputs by storing the truth table in SRAM.

A finite state machine where outputs depend on both current state and current inputs.

A device or circuit that stores digital data for later retrieval.

A technique where peripheral registers are accessed through the same address space as memory.

A cache coherence protocol tracking line states as Modified, Exclusive, Shared, or Invalid.

An unstable state where a flip-flop's output is undefined, occurring when setup or hold time is violated.

The hardware implementation of an ISA, defining how instructions are executed internally.

A passive testbench component that observes a DUT interface and reconstructs protocol transactions for logging, coverage, and checking.

A finite state machine where outputs depend only on the current state, not directly on inputs.

The bit position with the largest weight in a binary number, typically the leftmost bit.

A combinational circuit that selects one of multiple inputs and routes it to a single output based on select signals.

A logic gate that outputs the complement of AND—low only when all inputs are high.

A textual description of circuit connectivity, listing components and their connections.

A SystemVerilog assignment (<=) that schedules updates for the end of the time step, enabling correct sequential logic modeling.

A logic gate that outputs the complement of OR—high only when all inputs are low.

An encoding scheme where exactly one bit is high among a group, with each state represented by a single active bit position.

A circuit that generates a single output pulse in response to an input edge or level change.

The portion of an instruction that specifies the operation to be performed.

Rules governing the sequence in which memory operations become visible to different observers in a system.

The condition when an arithmetic result exceeds the representable range, causing incorrect results.

A structured unit of transmitted data that contains both payload and control information such as headers, length, or checksums.

A circuit that determines whether an input sequence reads the same forward and backward.

A circuit that accepts multiple bits in parallel and transmits them one bit at a time over successive clock cycles.

Design technique using parameters to create configurable, reusable modules with variable widths, depths, or features.

An error detection bit added to data, making the total number of 1s either even (even parity) or odd (odd parity).

An algorithm or circuit that detects whether a number is a perfect square (the square of an integer).

Hardware registers that count events (instructions, cache misses, cycles) for performance analysis and profiling.

A hardware component that provides I/O or specialized functionality, connected to the processor via bus interfaces.

A technique where multiple instructions execute simultaneously by dividing execution into stages, each handling a different instruction.

The physical design step that positions cells and creates wiring to implement a synthesized netlist.

A value that holds the address of a memory location, enabling indirect access to data.

The electrical energy used by a circuit per unit time, comprising dynamic and static components.

A ranking that determines service order when multiple requestors compete for a shared resource.

The semiconductor manufacturing technology used to fabricate integrated circuits, characterized by feature size.

A digital circuit that executes instructions, fetching, decoding, and performing operations on data.

A register that holds the address of the next instruction to be fetched.

The time for a signal change at a gate input to cause the corresponding change at its output.

A set of rules governing communication between hardware components, defining signal meanings and sequences.

A brief signal assertion, typically one clock cycle wide, indicating an event or trigger.

An ARM protocol for power state handshaking between a power controller and peripheral devices.

Memory that allows reading and writing to any address with similar latency, regardless of access pattern.

A group of flip-flops that store a multi-bit value, typically controlled by a common clock and enable.

An array of registers with multiple read and write ports, forming the processor's fast storage.

The rule a cache uses to decide which existing line to evict when a new line must be inserted into a full set.

A signal that forces circuit elements to known initial states, ensuring deterministic power-on behavior.

A processor design philosophy emphasizing simple instructions that execute quickly, enabling pipelining.

An open-source instruction set architecture based on RISC principles, free to implement without licensing fees.

An arbitration scheme that grants access to requestors in circular order, ensuring fairness.

An abstraction level describing digital circuits in terms of registers and the combinational logic transferring data between them.

A filter that computes the mean of the most recent N samples, smoothing data by attenuating high-frequency variations.

A graphical representation of a circuit showing components and their interconnections.

A testbench component that keeps a parallel reference model and checks DUT outputs against expected values on every transaction.

A counter that automatically reloads a configured value upon reaching zero or a terminal count.

An FSM that identifies a specific pattern in a serial input stream, asserting an output when the pattern occurs.

A circuit whose output depends on both current inputs and past history, incorporating memory elements.

The minimum time before the clock edge during which the data signal must be stable for reliable capture.

A chain of flip-flops where data shifts from one stage to the next on each clock cycle.

The process of increasing the bit width of a signed number while preserving its value by replicating the sign bit.

The process of executing a hardware model to verify behavior before physical implementation.

A single-entry buffer that decouples pipeline stages, enabling ready signal registration for timing closure.

An integrated circuit combining processor(s), memory, peripherals, and interconnect on a single chip.

Memory using bistable circuits (flip-flop-like) to store bits, providing fast access without refresh.

A pre-designed SRAM block provided as a hardened memory instance for use in ASIC or SoC designs.

A pre-designed, pre-characterized logic cell used as a building block in ASIC design.

A circuit that transitions through defined states based on inputs, producing outputs corresponding to each state or transition.

A circuit that safely transfers signals between different clock domains, mitigating metastability.

A digital circuit where all state changes are coordinated by a common clock signal.

A reset signal that takes effect only on the active clock edge, not immediately.

The automated transformation of HDL code into a gate-level netlist optimized for specific constraints.

An IEEE standard hardware description and verification language extending Verilog with advanced features.

The portion of a cache pipeline responsible for reading tags and checking whether the requested address matches a stored cache line.

A simulation environment that drives inputs to a design under test (DUT) and checks its outputs for correctness.

The rate of data processed or operations completed per unit time, measuring sustained performance.

The analysis and verification that signals arrive at destinations within required time windows.

A high-level object representing one protocol operation, such as a read, write, packet, or command, used by verification components instead of raw signal toggles.

A logic state (high-impedance or 'Z') where a driver disconnects from a bus, allowing other drivers to control it.

A table listing all possible input combinations and their corresponding outputs for a combinational function.

A signed number representation where negation is computed by inverting all bits and adding one.

The condition when a result is smaller than the minimum representable value, often occurring in subtraction or counters.

A handshake protocol where valid indicates data presence and ready indicates receiver acceptance, with transfer occurring when both are asserted.

The process of ensuring a design meets its specification through simulation, formal methods, and testing.

A hardware description language widely used for digital design and verification, now largely superseded by SystemVerilog.

A hardware description language with Ada-like syntax, offering strong typing and used heavily in aerospace and European designs.

A cache that indexes its sets using virtual address bits but tags its lines with physical addresses — "Virtually Indexed, Physically Tagged".

Reducing supply voltage to decrease power consumption, trading off performance.

A graphical representation of signal values over time, used for debugging and analyzing circuit behavior.

A signal type in Verilog/SystemVerilog representing a physical connection driven by continuous assignments or module outputs.

The natural data unit for a processor, typically 32 or 64 bits, defining register and bus width.

A logic gate that outputs high when inputs differ—one input high and one low—and low when inputs match.

An educational RISC-V processor implementation used in QuickSilicon courses to teach processor design fundamentals.

Simulation where combinational logic is modeled with zero propagation delay, showing functional behavior without timing effects.