Architecture
Cache Coherence
Protocols ensuring all processors see a consistent view of shared memory despite having private caches.
Detailed Explanation
When multiple processors cache the same memory location, writes by one processor must be visible to others. Coherence protocols track cache line states (Modified, Exclusive, Shared, Invalid—MESI) and broadcast or snoop transactions to maintain consistency.
Directory-based protocols scale better than snooping for many-core systems. Write-through caches simplify coherence but waste bandwidth. Write-back caches are more efficient but require more complex protocols.