HDL Concepts
Verilog
A hardware description language widely used for digital design and verification, now largely superseded by SystemVerilog.
Detailed Explanation
Verilog (IEEE 1364) introduced the module/port abstraction for hierarchical design. It supports behavioral modeling (always blocks), structural modeling (gate instantiation), and dataflow (continuous assignment). Verilog is case-sensitive with C-like syntax.
Verilog-2001 added ANSI-style ports and other improvements. Verilog-2005 was the last standalone version before merger with SystemVerilog. Legacy designs still use Verilog; new designs typically use SystemVerilog.