Day 1

Day 2

Day 3

Day 4

Day 5

Day 6

Day 7

Day 8

Day 9

Day 10

Day 11

Day 12

Day 13

Day 14

Day 15

Day 16

Day 17

Day 18

Day 19

Day 20

Day 21

Bonus Problem 1

# Day 11
Design and verify a 4-bit parallel to serial converter with valid and empty indications

## Interface Definition
The module should have the following interface:

```verilog
input     wire      clk,
input     wire      reset,

output    wire      empty_o,    -> Should be asserted when all of the bits are given out serially
input     wire[3:0] parallel_i, -> Parallel input vector
  
output    wire      serial_o,   -> Serial bit output
output    wire      valid_o     -> Serial bit is valid
```

## Coding Exercise
You're expected to code both the RTL and testbench for the problem. Your testbench should include
the stimulus and checkers.

### NOTE
The testcase will show PASSED as long as the RTL and testbench compile, but it doesn't
imply that the implemented logic is correct.

If you're interested in learning more about RTL Design and don't want to worry about implementing
the checks or the testbench code then I'd recommend the [Hands-on RTL Design](https://quicksilicon.in/course/rtl-design/?utm_source=quicksilicon&utm_medium=21DaysofRT&utm_campaign=cross-link) course.
The course contains 25 RTL Design problems to help improve your design skills and comes with a
2-part video solution for every problem.

## Challenge
Try solving [this](https://quicksilicon.in/course/rtl-design/module/parallel-to-serial) problem which deals with designing a parameterised parallel to serial converter with
valid-ready interface on both paralle and the serial interface.


## RTL
```verilog
// Parallel to serial with valid and empty

module day11 (
  input     wire      clk,
  input     wire      reset,

  output    wire      empty_o,
  input     wire[3:0] parallel_i,
  
  output    wire      serial_o,
  output    wire      valid_o
);

  // Shift register for the conversion
  logic [3:0] shift_ff;
  logic [3:0] nxt_shift;

  always_ff @(posedge clk or posedge reset)
    if (reset)
      shift_ff <= 4'h0;
    else
      shift_ff <= nxt_shift;

  // Take the parallel input when empty
  // Otherwise give the data out serially
  assign nxt_shift = empty_o ? parallel_i :
                               {1'b0, shift_ff[3:1]};

  assign serial_o = shift_ff[0];

  // Maintain a counter to drive valid and empty
  logic [2:0] count_ff;
  logic [2:0] nxt_count;

  always_ff @(posedge clk or posedge reset)
    if (reset)
      count_ff <= 3'h0;
    else
      count_ff <= nxt_count;

  // Count goes to zero when it reaches 4 (as all data given out)
  assign nxt_count = (count_ff == 3'h4) ? 3'h0 :
                                          count_ff + 3'h1;

  // Valid when count greater than 0
  assign valid_o = |count_ff;

  // Empty when count_ff == 0
  assign empty_o = (count_ff == 3'h0);

endmodule
```
## TB
```verilog
module day11_tb ();

  logic      clk;
  logic      reset;

  logic      empty_o;
  logic[3:0] parallel_i;
  logic      serial_o;
  logic      valid_o;

  day11 DAY11 (.*);

  // Clock
  always begin
    clk = 1'b1;
    #5;
    clk = 1'b0;
    #5;
  end

  // Stimulus
  initial begin
    reset <= 1'b1;
    parallel_i <= 4'h0;
    @(negedge clk);
    reset <= 1'b0;
    @(posedge clk);
    for (int i=0; i<32; i=i+1) begin
      parallel_i <= $urandom_range(0, 4'hF);
      @(posedge clk);
    end
    $finish();
  end

endmodule
```
