Day 2

Day 2

Design and verify various flavours of a D flip-flop

Interface Definition

The module should have the following interface:

input     logic      clk,
input     logic      reset,

input     logic      d_i,         -> D input to the flop

output    logic      q_norst_o,   -> Q output from non-resettable flop
output    logic      q_syncrst_o, -> Q output from flop using synchronous reset
output    logic      q_asyncrst_o -> Q output from flop using asynchrnoous reset

Coding Exercise

You're expected to code both the RTL and testbench for the problem. Your testbench should include the stimulus and checkers.

Did you notice the lint error? Do you think the lint error is expected and can be ignored for this case?

NOTE

The testcase will show PASSED as long as the RTL and testbench compile, but it doesn't imply that the implemented logic is correct.

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