Sequential Design
Flip-Flop
A bistable circuit that stores one bit of data, changing state on clock edges.
Detailed Explanation
Flip-flops are edge-triggered—they sample inputs and update outputs only on clock transitions. This differs from latches, which are level-sensitive. The edge-triggered behavior ensures clean state transitions and simplifies timing analysis.
Types include D flip-flop (direct data capture), JK flip-flop (toggle capability), and T flip-flop (toggle on high input). D flip-flops dominate modern design due to simpler behavior and synthesis.