Sequential Design
D Flip-Flop
A fundamental memory element that captures its data input on a clock edge and holds the value until the next clock edge.
Detailed Explanation
The D flip-flop (DFF) is the building block of sequential logic. On the active clock edge, the output Q takes the value of input D and holds it. This creates a one-cycle delay, essential for pipelining and state storage.
Variants include D flip-flops with asynchronous reset (immediate clear), synchronous reset (clear on next clock), and enable (update only when enabled). The flip-flop's setup and hold times define when D must be stable relative to the clock.
Code Example
systemverilog
// D flip-flop with async reset and enable
module dff_en (
input logic clk, reset, en, d,
output logic q
);
always_ff @(posedge clk or posedge reset) begin
if (reset)
q <= 1'b0;
else if (en)
q <= d;
end
endmodule