Day 1

Day 2

Day 3

Day 4

Day 5

Day 6

Day 7

Day 8

Day 9

Day 10

Day 11

Day 12

Day 13

Day 14

Day 15

Day 16

Day 17

Day 18

Day 19

Day 20

Day 21

Bonus Problem 1

# Day 5
Design and verify an 8-bit odd counter

## Interface Definition
- Counter should reset to a value of 8'h1
- Counter should increment by 2 on every cycle
- The module should have the following interface:

```verilog
input     wire        clk,
input     wire        reset,

output    logic[7:0]  cnt_o
```

## Coding Exercise
You're expected to code both the RTL and testbench for the problem. Your testbench should include
the stimulus and checkers.

### NOTE
The testcase will show PASSED as long as the RTL and testbench compile, but it doesn't
imply that the implemented logic is correct.

If you're interested in learning more about RTL Design and don't want to worry about implementing
the checks or the testbench code then I'd recommend the [Hands-on RTL Design](https://quicksilicon.in/course/rtl-design/?utm_source=quicksilicon&utm_medium=21DaysofRT&utm_campaign=cross-link) course.
The course contains 25 RTL Design problems to help improve your design skills and comes with a
2-part video solution for every problem.


## RTL
```verilog
// Odd counter

module day5 (
  input     wire        clk,
  input     wire        reset,

  output    logic[7:0]  cnt_o
);


  logic [7:0] nxt_cnt;

  always_ff @(posedge clk or posedge reset)
    if (reset)
      cnt_o <= 8'h1;
    else
      cnt_o <= nxt_cnt;

  assign nxt_cnt = cnt_o + 8'h2;

endmodule
```
## TB
```verilog
// Simple TB

module day5_tb ();

  logic clk;
  logic reset;

  logic [7:0] cnt_o;

  day5 DAY5 (.*);

  always begin
    clk = 1'b0;
    #5;
    clk = 1'b1;
    #5;
  end

  initial begin
    reset <= 1'b1;
    @(posedge clk);
    @(posedge clk);
    reset <= 1'b0;
    for (int i=0; i<128; i++)
      @(posedge clk);
    $finish();
  end

endmodule
```
