Day 1

Day 2

Day 3

Day 4

Day 5

Day 6

Day 7

Day 8

Day 9

Day 10

Day 11

Day 12

Day 13

Day 14

Day 15

Day 16

Day 17

Day 18

Day 19

Day 20

Day 21

Bonus Problem 1

# Day 6
Design and verify a simple shift register

## Interface Definition
The module should have the following interface:

```verilog
input     wire        clk,
input     wire        reset,
input     wire        x_i,  -> Serial input

output    wire[3:0]   sr_o  -> Shift register output
```

## Coding Exercise
You're expected to code both the RTL and testbench for the problem. Your testbench should include
the stimulus and checkers.

### NOTE
The testcase will show PASSED as long as the RTL and testbench compile, but it doesn't
imply that the implemented logic is correct.

If you're interested in learning more about RTL Design and don't want to worry about implementing
the checks or the testbench code then I'd recommend the [Hands-on RTL Design](https://quicksilicon.in/course/rtl-design/?utm_source=quicksilicon&utm_medium=21DaysofRT&utm_campaign=cross-link) course.
The course contains 25 RTL Design problems to help improve your design skills and comes with a
2-part video solution for every problem.


## RTL
```verilog
// Simple shift register
module day6(
  input     wire        clk,
  input     wire        reset,
  input     wire        x_i,      // Serial input

  output    wire[3:0]   sr_o
);

  logic [3:0] sr_ff;
  logic [3:0] nxt_sr;

  always_ff @(posedge clk or posedge reset)
    if (reset)
      sr_ff <= 4'h0;
    else
      sr_ff <= nxt_sr;

  assign nxt_sr = {sr_ff[2:0], x_i};

  assign sr_o = sr_ff;

endmodule
```
## TB
```verilog
module day6_tb ();

  logic         clk;
  logic         reset;
  logic         x_i;
  logic [3:0]   sr_o;

  day6 DAY6 (.*);

  // generate clock
  always begin
    clk = 1'b1;
    #5;
    clk = 1'b0;
    #5;
  end

  // Stimulus
  initial begin
    reset <= 1'b1;
    x_i <= 1'b0;
    @(posedge clk);
    reset <= 1'b0;
    @(posedge clk);
    for (int i=0; i<16; i=i+1) begin
      x_i <= $random%2;
      @(posedge clk);
    end
    $finish();
  end

endmodule
```
