Sequential Design
Counter
A sequential circuit that cycles through a sequence of states, typically incrementing or decrementing a binary value.
Detailed Explanation
Counters are fundamental building blocks for timing, sequencing, and address generation. Binary counters increment by 1 each clock. Up/down counters can count in either direction based on a control signal. Modulo-N counters wrap after reaching N-1.
Gray code counters change only one bit per transition, useful for clock domain crossing. Ring counters shift a single 1 through a register. Johnson counters use inverted feedback for a 2N-state sequence.
Code Example
systemverilog
// Up/down counter with enable
module counter #(parameter WIDTH = 8) (
input logic clk, reset, en, up_down,
output logic [WIDTH-1:0] count
);
always_ff @(posedge clk or posedge reset) begin
if (reset)
count <= '0;
else if (en)
count <= up_down ? count + 1'b1 : count - 1'b1;
end
endmodule