Introduction - RISC-V

Computer Architecture

RISC-V ISA

Introduction to YARP

YARP Fetch

YARP Decode

YARP Register File

YARP Execute

YARP Data Memory

YARP Control

YARP Branch Control

YARP Top

Assessment

This tutorial would cover one of the basic data memory element for the YARP core i.e. the Data Memory.
But before jumping into the details, here is a quick recap of the current state of the YARP core. The
core has units ready to fetch instruction from instruction memory, decode the instruction bytes, setup
the source and destination register and also has the ALU unit to perform functions on the data. This
tutorial would add the data memory unit to allow the memory instructions (like loads and stores) to
access the data memory with the needed operation. The RISC-V ISA specifies various sub-operations which
the load and store instructions can perform. It would be good to review section 2.6 Load and Store Instructions
of the ISA before starting.

## Data Memory
The data memory is needed to read or write data generated by the processor to the memory. The data
memory acts like a storage area where the processor can write data generated after performing a series
of operation. The data can be also be retrived by performing the load instruction which reads the data
