Introduction - RISC-V

Computer Architecture

RISC-V ISA

Introduction to YARP

YARP Fetch

YARP Decode

YARP Register File

YARP Execute

YARP Data Memory

YARP Control

YARP Branch Control

YARP Top

Assessment

Congratulations on making it so far and finally to the last module which puts all of the things together.
The top module would complete the *Y*et *A*nother *R*ISC-V *P*rocessor core. The top module essentially
puts all of the different pieces of puzzles together. This means instantiating the various sub-modules
designed in the previous lessons and designing the muxes needed for connecting the various outputs from
one unit to the other.

## YARP Top
The YARP Top would include all of the muxes needed to connect various output signals from one unit
to the other. The mux selects would be driven via the control unit output and the module would
also include the flops needed for storing the current Program Counter. The logic for the next
value of the program counter would also be part of the top module. Finally, the module would
include the top level interface of the processor. 
