Instruction Fetch
The first pipeline stage of a processor, where the next instruction is read from instruction memory using the program counter.
Detailed Explanation
Instruction fetch is the stage that kicks off every cycle of useful work in a CPU. The processor uses the program counter (PC) as an address into instruction memory and reads back the encoded instruction bits. At the end of the stage, the PC is updated — either by adding the instruction width for the sequential case, or by loading a branch target when the control unit redirects the flow.
In a single-cycle implementation fetch happens combinationally alongside every other stage; in a pipelined processor it becomes its own stage with a dedicated IF/ID pipeline register. Fetch is also where front-end hazards first appear: a taken branch discovered later in the pipeline forces the IF stage to squash speculative instructions and redirect the PC.
Industry Context
Fetch-stage design decisions dominate front-end performance. High-performance cores add branch predictors, instruction caches, and fetch buffers to feed the pipeline even when the PC stream is irregular.
Code Example
// Minimal fetch stage: read instruction, update PC
module fetch (
input logic clk, rst_n,
input logic branch_taken,
input logic [31:0] branch_target,
output logic [31:0] pc,
output logic [31:0] instr,
input logic [31:0] imem_rdata
);
logic [31:0] pc_q;
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) pc_q <= 32'h0;
else if (branch_taken) pc_q <= branch_target;
else pc_q <= pc_q + 32'd4;
assign pc = pc_q;
assign instr = imem_rdata; // imem addressed by pc_q
endmodule