Architecture
Instruction
A single operation command in a processor's ISA, specifying an operation and its operands.
Detailed Explanation
Instructions encode the operation (ADD, LOAD, BRANCH), source operands (registers, immediates), and destination (register, memory). Instruction formats vary by ISA—RISC architectures use fixed-length instructions; CISC uses variable length.
Instructions flow through the processor pipeline: fetch, decode, execute, memory, writeback. Each stage performs its function, allowing multiple instructions to be in-flight simultaneously.