Threads and Memories

PROBLEM STATEMENT:
Earlier, we learnt how many designs have a time based (or time domain multiplexed) architecture where multiple unique threads share the same logic resource.
In this design, we tackle the challenge of storing,retrieving and updating information that is unique to each thread.

In this design, the information to be stored is a 32-bit counter value.
There can be up to 8 threads/channels, meaning 8 unique counter values to be maintained.

Each counter starts off with the value 0 at reset. Different kinds of updates can be done to these counters as indicated by the update_type_i input signal.

There is a SRAM module in the design which has a write port and a read port.
The write port can accept a write request every cycle and has a write latency of 1 clock cycle.

The read port can accept a read request every cycle and has a read latency of 2 clock cycles. I.e after a read address is passed along with a read enable signal, it takes 2 clocks for the corresponding data to be available at the read port.

Updated value of the counter is sent to the output. Hence the testbench expects a 2 clock delay from input to output of this module.