Introduction

Running Simulations

Combinatorial Logic

Sequential Logic

D Flip-Flop

D Flip-Flop with Enable

Counter

Up-down Counter

Self Reloading Counter

Shift Register

We have discussed about the basic building blocks of any complex digital ciruits:
- Combinational Logic
- Sequential Logic

This video discusses about the most widely used sequential element i.e. D flip-flop.

We would be designing the three different falvours of a D flip-flop:
- Non resettable
- Synchronous Reset
- Asynchronous Reset

All the flops should be positive edge triggered with active high resets (if any).

This video also discusses the generated waveforms in detail to explain the flop behaviour.

## Interface Definition

```verilog
d_i           => The input to the flop D-pin
q_norst_o     => Output from the non-resettable flop
q_syncrst_o   => Output from the flop with synchronous reset
q_asyncrst_o  => Output from the flop with asynchronous reset
```


We have discussed about the basic building blocks of any complex digital ciruits:
- Combinational Logic
- Sequential Logic

This video discusses about the most widely used sequential element i.e. D flip-flop.

We would be designing the three different falvours of a D flip-flop:
- Non resettable
- Synchronous Reset
- Asynchronous Reset



## System Verilog

```verilog
// --------------------------------------------------------
// Copyright (C) quicksilicon.io - All Rights Reserved
//
// Unauthorized copying of this file, via any medium is
// strictly prohibited
// Proprietary and confidential
// --------------------------------------------------------

// --------------------------------------------------------
// DFF - RTL
// --------------------------------------------------------

module dff (
  input   logic        clk,
  input   logic        reset,

  input   logic        d_i,

  output  logic        q_norst_o,
  output  logic        q_syncrst_o,
  output  logic        q_asyncrst_o

);

  // --------------------------------------------------------
  // Main logic
  // --------------------------------------------------------
  // No reset
  always_ff @(posedge clk)
    q_norst_o <= d_i;

  // Sync reset
  always_ff @(posedge clk)
    if (reset)
      q_syncrst_o <= 1'b0;
    else
      q_syncrst_o <= d_i;

  // Async reset
  always_ff @(posedge clk or posedge reset)
    if (reset)
      q_asyncrst_o <= 1'b0;
    else
      q_asyncrst_o <= d_i;

endmodule
```
