SystemVerilog Testbench Introduction

SystemVerilog Testbench Architecture

APB Interface

APB Transaction

APB Generator

APB Driver

APB Driver Phase 2

APB Monitor

APB Scoreboard

APB Environment

APB Testbench Top

RISC-V Processor (YARP) Interface

YARP Transaction

YARP Generator

YARP Driver

YARP Data Memory Model

YARP Monitor

YARP Scoreboard

YARP Testbench Top

DVCon 26 Hackathon Problem

Array Sum Limit

Array Index Sum Limit

Ball Draw No Repeat

Conditional Even Probability

Even Odd Index Value

Five Consecutive Ones

Frequency Constraint

Grouped Ones

Index Value Range

Leap Year

Matrix Rotation

Non Adjacent Ones

Power of 4

Dynamic Ranges

Recent Four Unique

Row Max Unique

Subarray Max Sum

Three Duplicates Only

Tic Tac Toe

Unique 3D Array

Weighted Popcount

Unique Sum

Split Array into Queues

For the `yarp_monitor` component of the YARP CPU testbench, we would be implementing the same mechanism
as we did for the `apb_slave_monitor` component in the `apb_testbench` module. The monitor would be used to
monitor the YARP CPU's instruction and data memory interfaces and would then send those transactions to the
scoreboard for checking. In the case of the `yarp_monitor`, the mailbox would be written every cycle and the
valid/ready handshake would be done in the scoreboard. This is needed since the way the instruction and the
data memory interfaces are implemented in the YARP CPU, the scoreboard would need access to the valid on the
data memory interface in order to check the transactions correctly.
