YARP Transaction

In the last module we discussed the YARP RISC-V Processor RTL which is our design under test. We also implemented the SystemVerilog based interface to communicate between the RTL and the Testbench. In this module we would look into the Transaction Class.

Transaction Class

Like we saw in the APB System Testbench design, the first component in the testbench is the transaction class. The transaction class will be used to create random stimulus for our testbench which would be driven to the YARP CPU via the driver. Since the testbench would be responsible for driving all the inputs to the design, the transaction class should be able to randomize all of the input signals while up-holding all the constraints which may apply to any of the signals.

Testbench_Architecture

This would imply that the following input signals should be randomized along with any constraints:

• instr_mem_rd_data_i : The read data from the instruction memory
• instr_mem_ready_i : Indicates the ready from the instruction memory along with read data
• data_mem_rd_data_i : The read data from the data memory
• data_mem_ready_i : Indicates the ready from the data memory along with read data

Transaction Class Constraints

Now, that we know that the transaction class should be able to randomize the input signals, we also need to understand the constraints which apply to these signals. The constraints are as follows:

• instr_mem_rd_data_i should be a valid instruction as per the RV32I instruction set architecture
• instr_mem_ready_i should be asserted whenever the instruction memory is ready
• data_mem_rd_data_i should be a valid data read from the data memory
• data_mem_ready_i should be asserted whenever the data memory is ready

For the transaction class, we would only be implementing the constraints for the instr_mem_rd_data_i signal. The reason we would not be implementing the constraints for the data_mem_rd_data_i signal is because the data memory would also be written by the YARP core and hence the data memory model would need to be able to read the last data written by the YARP core and can't really be randomized. As we would later see, the data_mem_rd_data_i signal would eventually be driven off by a data memory model which we would implement later.