Architecture
Arbiter
A circuit that manages access to a shared resource among multiple requestors, granting access based on a priority or fairness scheme.
Detailed Explanation
Arbiters resolve contention when multiple agents want simultaneous access to a shared resource like a bus, memory port, or functional unit. Common arbitration schemes include fixed priority (simple but can starve low-priority requestors), round-robin (fair but adds complexity), and weighted round-robin (configurable fairness).
A well-designed arbiter must be fast (single-cycle grant for performance), fair (prevent starvation), and handle edge cases (no requestors, all requestors). The grant signal typically gates the winning requestor's access to the shared resource.
Code Example
systemverilog
// Fixed-priority arbiter (port 0 highest priority)
module arbiter #(parameter N = 4) (
input logic [N-1:0] req_i,
output logic [N-1:0] gnt_o
);
logic [N-1:0] priority_mask;
assign priority_mask[0] = 1'b0;
genvar i;
generate
for (i = 0; i < N-1; i++) begin
assign priority_mask[i+1] = priority_mask[i] | req_i[i];
end
endgenerate
assign gnt_o = req_i & ~priority_mask;
endmodule