APB Slave

The APB slave is the passive side of the bus. It samples `psel` to know it has been selected, then looks at `paddr`, `pwrite`, and — on access-phase — either captures `pwdata` or drives `prdata`. A compliant slave must assert `pready` within a bounded number of cycles, and on error it can assert `pslverr` to signal the master that the transaction failed.

Most APB slaves in real silicon wrap a small register bank — status, configuration, interrupt-mask registers — so the slave's internal logic is dominated by an address decoder plus a column of flops. The hard work isn't the protocol itself but the register bank's *semantics*: which bits are RW, which are RO, which are write-one-to-clear, and which trigger side effects on write. Tools like SystemRDL exist to generate this boilerplate from a register description.