HDL Concepts
Blocking Assignment
A SystemVerilog assignment (=) that executes sequentially, completing before the next statement begins.
Detailed Explanation
In procedural blocks, blocking assignments execute in order like traditional programming. The right-hand side is evaluated and assigned to the left-hand side immediately. Subsequent statements see the updated value.
Blocking assignments are appropriate for combinational logic in always_comb blocks where order doesn't matter for synthesis but aids readability. Using blocking assignments in clocked (always_ff) blocks is discouraged as it can cause simulation-synthesis mismatches.
Code Example
systemverilog
// Blocking assignments in combinational logic - OK
always_comb begin
temp = a & b; // temp gets value immediately
result = temp | c; // uses updated temp value
end
// DON'T use blocking in sequential logic
always_ff @(posedge clk)
q = d; // Bad practice - use <= instead