HDL Concepts
Non-Blocking Assignment
A SystemVerilog assignment (<=) that schedules updates for the end of the time step, enabling correct sequential logic modeling.
Detailed Explanation
Non-blocking assignments evaluate the right-hand side immediately but defer the left-hand side update. All non-blocking assignments in a time step see the old values, and all updates occur simultaneously. This models flip-flop behavior correctly.
Using non-blocking assignments in always_ff blocks prevents race conditions where read and write order would affect results. All flip-flops effectively sample simultaneously, matching real hardware behavior.
Code Example
systemverilog
// Non-blocking assignments - correct for sequential logic
always_ff @(posedge clk) begin
a <= b; // a gets old value of b
b <= a; // b gets old value of a
// Result: a and b swap values
end
// If we used blocking (wrong!):
always_ff @(posedge clk) begin
a = b; // a gets b
b = a; // b gets NEW a (which is old b)
// Result: both get old b value - not a swap!
end