Timing
Clock
A periodic signal that synchronizes operations in a digital circuit, triggering state changes on its edges.
Detailed Explanation
The clock is the heartbeat of synchronous digital systems. All flip-flops sample their inputs on the clock edge (rising, falling, or both), ensuring coordinated state updates. Clock frequency determines the system's speed, limited by the longest combinational path between registers.
Clock distribution is a significant challenge—the clock must reach all flip-flops with minimal skew (variation in arrival time). Clock trees use buffers arranged in H-trees or mesh structures. Clock gating saves power by stopping clocks to idle blocks.
Code Example
systemverilog
// Clock divider - divide by 2
always_ff @(posedge clk or posedge reset) begin
if (reset)
clk_div2 <= 1'b0;
else
clk_div2 <= ~clk_div2;
end