Digital Logic
Full Adder
A combinational circuit that adds three single bits (two operands plus carry-in) producing sum and carry-out.
Detailed Explanation
The full adder is the building block for multi-bit addition. It computes sum = A ⊕ B ⊕ Cin and Cout = (A·B) + (Cin·(A⊕B)). Chaining full adders creates ripple-carry adders, though carry propagation limits speed.
Full adders can be implemented with two half adders and an OR gate, or directly from NAND/NOR gates. FPGA synthesis often maps full adders to dedicated carry logic for efficiency.
Code Example
systemverilog
module full_adder (
input logic a, b, cin,
output logic sum, cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));
endmodule