Timing
Hazard
A condition where circuit behavior differs from expected due to timing or structural issues.
Detailed Explanation
Static hazards occur when a signal that should remain constant shows a momentary glitch due to unequal path delays. Dynamic hazards show multiple transitions when one is expected. Data hazards in pipelines occur when instructions depend on results not yet available.
In combinational logic, hazards are timing-related glitches. In pipelines, hazards (RAW, WAR, WAW) affect instruction scheduling. Hazard avoidance uses careful design, redundant logic, or pipeline stalls/forwarding.