Timing
Glitch
A brief, unwanted signal transition caused by unequal propagation delays through combinational logic paths.
Detailed Explanation
When inputs to combinational logic change, outputs may momentarily show incorrect values before settling. For example, if A and B in A AND (NOT A) don't change simultaneously, a brief high pulse (glitch) can occur.
Glitches are harmless in synchronous designs if they settle before the clock edge. However, glitches can cause problems if they trigger asynchronous logic, clock gating cells, or cross into other clock domains.