Digital Logic
Inverter
A logic gate that produces the complement (NOT) of its input—0 becomes 1, 1 becomes 0.
Detailed Explanation
The inverter is the simplest logic gate, implementing Boolean NOT. In CMOS, it uses one NMOS and one PMOS transistor in series between VDD and ground. Inverter chains form delay elements.
Inverter delay and drive strength are fundamental characterization parameters. Cascaded inverters of increasing size (inverter chain) drive heavy loads while maintaining signal integrity.