Implementation
Place and Route (P&R)
The physical design step that positions cells and creates wiring to implement a synthesized netlist.
Detailed Explanation
Placement assigns physical locations to each cell, optimizing for timing, wire length, and routability. Routing creates metal connections between cells. Iterative optimization meets timing constraints while minimizing area and power.
P&R is computationally intensive—large designs take hours to days. The result is a layout ready for manufacturing (ASIC) or bitstream generation (FPGA). Timing analysis after P&R uses actual wire delays.