Implementation
Netlist
A textual description of circuit connectivity, listing components and their connections.
Detailed Explanation
Netlists represent designs at various abstraction levels. RTL netlists describe modules and their interconnections. Gate-level netlists show individual gates and their wiring. Post-layout netlists include parasitic elements.
Netlist formats include Verilog (structural), EDIF, SPICE (for analog), and LEF/DEF (physical). Synthesis produces gate-level netlists from RTL. Place-and-route consumes and produces netlists.