Sequential Design
Register
A group of flip-flops that store a multi-bit value, typically controlled by a common clock and enable.
Detailed Explanation
Registers are the fundamental storage elements in digital systems. They hold state between clock cycles—processor data, intermediate results, configuration values. Register width matches the data being stored.
Registers may include enable (update only when enabled), reset (clear to known value), and load (parallel input). Pipeline registers separate pipeline stages. Configuration registers hold system settings.
Code Example
systemverilog
// Parameterized register with enable and reset
module register #(parameter WIDTH = 8) (
input logic clk, reset, en,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q
);
always_ff @(posedge clk or posedge reset) begin
if (reset)
q <= '0;
else if (en)
q <= d;
end
endmodule