Protocols
Valid-Ready Protocol
A handshake protocol where valid indicates data presence and ready indicates receiver acceptance, with transfer occurring when both are asserted.
Detailed Explanation
The sender asserts valid when data is available; the receiver asserts ready when it can accept. Data transfers when valid AND ready are both high. The sender must hold data stable while valid is high until ready is seen.
This protocol is self-throttling—backpressure naturally occurs when the receiver lowers ready. It's the standard handshake for AMBA buses and streaming interfaces. Correctness requires following the protocol exactly—valid must not depend on ready (can cause deadlock).
Code Example
systemverilog
// Valid-ready handshake: transfer occurs when both high
wire transfer = i_valid & i_ready;
// Source must hold data stable until transfer
always_ff @(posedge clk) begin
if (transfer || !i_valid)
i_data <= next_data;
// Once valid, can only deassert on transfer
end
// Sink drives ready based on internal state
assign i_ready = !fifo_full;