Sequential Design
Shift Register
A chain of flip-flops where data shifts from one stage to the next on each clock cycle.
Detailed Explanation
Shift registers implement serial-to-parallel and parallel-to-serial conversion. Data enters at one end and moves through stages each clock. A 4-bit shift register takes 4 clocks to shift data from input to output end.
Applications include serial communication (UART shift registers), pattern generation/detection, and implementing delays. Bidirectional shift registers can shift left or right based on control.
Code Example
systemverilog
// N-bit shift register with serial input/output
module shift_reg #(parameter N = 8) (
input logic clk, reset, serial_in,
output logic serial_out,
output logic [N-1:0] parallel_out
);
logic [N-1:0] reg_q;
always_ff @(posedge clk or posedge reset) begin
if (reset)
reg_q <= '0;
else
reg_q <= {reg_q[N-2:0], serial_in};
end
assign serial_out = reg_q[N-1];
assign parallel_out = reg_q;
endmodule