Low Power
Clock Gating
A power-saving technique that disables the clock to idle circuit blocks, eliminating switching power.
Detailed Explanation
Dynamic power is proportional to switching activity. Clock gating stops the clock to registers that don't need to update, saving the power otherwise wasted on flip-flop clock inputs. Integrated clock gating cells (ICGs) ensure glitch-free clock enable.
Fine-grained gating (per register) offers maximum savings but high overhead. Coarse-grained gating (per block) is simpler to implement. Synthesis tools automatically insert clock gating when registers have enable conditions.