Finite State Machine (FSM) Definition, Meaning & Example - QuickSilicon

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Sequential Design

Finite State Machine (FSM)

A sequential circuit with a finite number of states, transitioning between states based on inputs and producing outputs.

Detailed Explanation

FSMs model control logic—protocol handlers, sequencers, and pattern detectors. Moore machines output based on state only; Mealy machines output based on state and inputs (faster response but more complex).

FSMs consist of state register (flip-flops holding current state), next-state logic (combinational, determines next state from current state and inputs), and output logic (generates outputs). State encoding (binary, one-hot, gray) affects area and timing.

Code Example

systemverilog

// Moore FSM for pattern detection (1011)
typedef enum logic [1:0] {S0, S1, S2, S3} state_t;
state_t state_q, state_d;

always_comb begin
  state_d = state_q;
  case (state_q)
    S0: state_d = in ? S1 : S0;
    S1: state_d = in ? S1 : S2;
    S2: state_d = in ? S3 : S0;
    S3: state_d = in ? S1 : S2;
  endcase
end

assign detected = (state_q == S3) && in;