Sequential Design
Latch
A level-sensitive storage element that passes input to output when enabled and holds when disabled.
Detailed Explanation
Unlike edge-triggered flip-flops, latches are transparent when enabled—output follows input. When disabled, the latch holds its last value. D latches are common; SR latches have set/reset inputs.
Latches are generally avoided in synchronous design because their level-sensitivity complicates timing analysis. Accidental latch inference (incomplete if statements or case statements in combinational blocks) is a common bug.
Code Example
systemverilog
// Unintended latch inference - DON'T DO THIS
always_comb begin
if (en)
q = d; // Missing else creates latch!
end
// Correct - explicitly assign all paths
always_comb begin
if (en)
q = d;
else
q = 1'b0; // Or use q = q for intentional latch
end